1. Field of the Invention
The present invention relates to a video output controller and a video card, and particularly, to a video output controller capable of programming a graphics processor.
2. Description of Related Art
Japanese Patent Laid Open Publication (Kokai) No. 2001-84217 discloses a DMA (direct memory access) circuit having a memory to store a plurality of source addresses and a source address register to hold a first one of the source addresses stored in the memory.
Japanese Patent Laid Open Publication (Kokai) No. 2002-132706 discloses a DMA transfer device having a transfer address storing unit to store a first address of a data block containing data for a plurality of lines to be DMA-transferred in response to an instruction from a CPU and a storage unit to store the number of data lines to be transferred.
Specification of U.S. Pat. No. 6202106B1 discloses an intelligent DMA controller (IDMAC) having a parameter block structure that includes an initial memory location and at least one pointer, which is based on the initial memory location, for a plurality of parameter locations (such as source addresses and destinations).
These DMA devices are constituted by hardware, and therefore, only allow a display resolution to be selected from a predetermined number of resolutions. Generally, frame buffers are secured in continuous areas in a memory, and therefore, data in the frame buffers must first be collected to form a frame when carrying out a collaborative rendering operation with, for example, a distributed shared memory computer system.